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EE Cadence Support

Cal Poly has been a member of the Cadence University Program since October 2010. The software has been operable since February 2012. Hardware was expanded to improve Cadence performance in October 2012. Due to the increase in number of students who needed to use the Cadence tools for senior/Master's projects and class projects, additional improvements were made Summer 2014 to allow for the support of 100 Cadence accounts. The system was moved to RedHat during Summer 2015 and updated to the newest Cadence tool versions. New tools were added to the suite including ADS abilities, plus additional Cadence tools were added. In Spring 2019, over 200 accounts were being supported without problem.

We use Cadence Design Systems, Inc. products in EE 431 (CAD of VLSI), EE 544 (Solid-state Electronics and VLSI Laboratory), senior projects, Master's projects, and faculty research. New labs for EE 307/347 (Digital Integrated Circuits) were developed for Winter 2018. We have taped out multiple chips through MOSIS. Cadence and MOSIS's generous support has contributed greatly to Cal Poly's integrated circuit program! 


In our program, we use and have used Cadence* products in research projects including: 

- ICs for clear circuits on contact lenses: Receiver, transmitter, wireless on-lens battery charging and display control

- MCML standard cell library for low noise applications 

- SRAM compiler 

- Low power clock distribution

- Blood glucose sensing circuit 

- UWB transceiver 

- Minimal area ADC research 

- Computer compiler 


Class projects include: 

- Bandgap voltage reference research

- SerDes circuits

- FPGA designs 

- PWM controller 

- PUC (Physically Unclonable Constant) circuitry 

- FinFET Switched Capacitor Amplifier 


Responsible Faculty and Support: 

The faculty member responsible for this webpage, technology files, and Cadence software support is Dr. Tina Smilkstein. Professors participating in evolving Cal Poly''s IC design track include Dr. John Oliver. Network technician Rob Randle maintains the hardware and is in charge of keeping the Cadence labs running smoothly. 


Cadence Tutorials: 

Starting up Cadence (pdf)

Tutorial 1: Schematic entry and simulation on Virtuoso using Spectre (pdf)

Tutorial 2: Custom layout, DRC, LVS, extraction

Tutorial 3: PCell layout from schematic, DRC, LVS, extraction, simulation (LVS and DRC additions to come) (pdf)

Tutorial 4: Verilog to silicon, Encounter, RTL compiler, extraction, DEF export, Virtuoso simulation

Tutorial 5: Floorplanning and pad frame



NCSU Wiki 

Digital VLSI Chip Design with Cadence and Synopsys CAD Tools


*Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA, 95134. 

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