Project Description
As the number of transistors per processor increases, per Moore’s Law, a processor’s demand for power also increases. The demand for improved processor performance has also increased. What’s more critical is that for energy efficiency and better performance and reliability, the operating voltage for processors has decreased to the range of 1V to 2V. This poses major design challenges for the dc-dc converter, known as a Voltage Regulator Module (VRM), that supplies power to these processors. Therefore, there is an urgent need for new topologies beyond the existing basic Multiphase Buck VRM topology that effectively addresses these design challenges.
There are several new VRM topologies currently being developed in the Power Electronics Lab at Cal Poly. Prototypes of two of these new topologies have been successfully built and tested. Results show promising performance which includes very low peak to peak output voltage ripple and extremely tight load and line regulation, while maintaining fast dynamic response. Cal Poly, through the Graduate and Research Office, has applied for US patents on the two new topologies. Other new topologies are currently being characterized and developed.
For further information, or if interested, please contact Dr. Taufik.
Dr. Taufik
taufik@calpoly.edu
